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Espressif Systems /ESP32-C6 /TWAI0 /BUS_TIMING_1

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Interpret as BUS_TIMING_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TIME_SEG1 0TIME_SEG2 0 (TIME_SAMP)TIME_SAMP

Description

Bit timing configuration register 1.

Fields

TIME_SEG1

The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode.
TIME_SEG2

The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode.
TIME_SAMP

1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data